Using System Generator to Design a Reconfigurable Video Encryption System
نویسندگان
چکیده
As FPGAs increase in size there is a need for improved productivity, and this includes new design flows and tools. System Generator, from Xilinx, is a high-level block-based design tool that offers bit and cycle accurate simulation. In this paper, we discuss the use of System Generator to design a reconfigurable video encryption system. It includes the design of the AES (Advanced Encryption System) and Enigma encryption cores. This paper also demonstrates the use of Nallatech block-sets within System Generator to provide a synthesisable link straight to hardware. As a result of using this design flow, we are able to efficiently implement our system and algorithms with a significant improvement on traditional design times, without compromise for performance or area.
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